A transistor may be produced in thin-film form, as is the case for example in microelectronic circuits. According to one possible design, the channel (produced in a semiconductor material) is separated from the gate by a first thin film (of insulating material) which constitutes the dielectric of the transistor.
The gate can therefore be produced in a second thin film superposed on the dielectric-forming first layer.
To define the lateral extension of the gate (that is to say its dimension in a direction perpendicular to the multilayer), one solution consists in using plasma etching, for example using an HBr/O2 etchant. According to this technique, explained here with reference to FIGS. 1 and 2, an etching mask 10 is deposited on the second layer 8 intended to form the gate. In this step, as is visible in FIG. 1, the various layers (especially the channel 4 produced here in the form of a thin film and the dielectric-forming second layer 6) have thicknesses that are essentially constant over their entire width. (For completeness, mention may also be made in the example described here of the buried layer 2 made of insulating material—the assembly comprising the buried layer 2 and the channel 4 being in this example produced by the SOI (silicon-on-insulator) technology).
When the structure that has just been described (shown in FIG. 1) undergoes the abovementioned plasma etching, the structure as shown in FIG. 2 is obtained. As desired, the plasma etching makes it possible to obtain a gate 12 of limited lateral extension by removal of the second layer 8 from the regions that are not covered by the etching mask 10.
However, it should be pointed out that, because of the small thickness of the dielectric-forming first layer 6, the plasma etching has caused the upper portions of the channel-forming layer 4 to be oxidized (with the exception of the gate 12, which prevents this oxidation), this having the effect of reducing the thickness of the channel-forming layer represented with its reduced thickness by the reference 4′ in FIG. 2. Such a phenomenon has for example been demonstrated in the article “Sub-0.1 μm gate etch processes: towards some limitations of the plasma technology?” by L. Desvoivres, L. Vallier and O. Joubert, J. Vac. Sci. Technol. B 18(1), January-February 2000.
FIG. 3 illustrates the transistor obtained by the process that has just been described and provided with its spacers 14. As anticipated, because of the phenomenon that has just been explained, the thickness of the channel 4′ is reduced beneath the spacers 14, resulting in a degradation in the performance of the transistor thus formed, especially by an increase in the channel access resistance which results in a reduction in the saturation current of the transistor.
This performance degradation is also further exacerbated when the lateral dimension of the gate decreases, which is the current tendency in microelectronics.